Flat panel displays have gradually replaced cathode ray tube (CRT) displays in display field, because they provide good quality images with little power consumption and are very thin. The flat panel display is usually used in a computer system by connected to a computer host and receives image signals from the computer host to display.
Referring to FIG. 10, a typical computer system 100 includes a computer host 110 and a flat panel display 120 connected to each other via a data transmitting line 130. The data transmitting line 130 is used to transmit image signals and other data signals from the computer host 110 to the flat panel display 120.
The flat panel display 120 includes a plurality of pixels arranged in an M×N matrix, wherein M represents a number of the pixels in a horizontal direction, and N represents a number of the pixels in a vertical direction. Thus, the flat panel display 120 has a fixed resolution of M×N, namely, a fixed horizontal resolution of M and a fixed vertical resolution of N. The flat panel display 120 can display an image signal having a resolution no more than M×N.
The computer host 110 can output image signals having different resolutions, such as 800×600, 1024×768, 1280×1024, and so on. A user can adjust the resolution of the image signal. Thus, the image signal output from the computer host 110 has a variable resolution, namely, a variable horizontal resolution and a variable vertical resolution.
If the flat panel display 120 has a fixed resolution of 1024×768, when an image signal output from the computer host 110 has a resolution of 1280×1024 or 800×600, the flat panel display 120 may be incompatible with the computer host 110. Thus, a display error or an image distortion phenomenon will occur.
A method for resolving the above problems is adjusting a timing of the image signal, namely, scaling the image signal, to make the resolution of the image signal match the fixed resolution of the flat panel display 120. Thus, the resolution of the image signal needs to be detected before scaled. Therefore, a scaler control circuit is usually needed in the flat panel display 120 to detect and scale the resolution of the image signal.
Referring to FIG. 11, a scaler control circuit 200 of the flat panel display 120 is shown. The scaler control circuit 200 includes a horizontal counter 210, a vertical counter 220, a decoder 230, a bypass controller 240, and a scaler unit 250. The horizontal counter 210 and the vertical counter 220 are used to determine the resolution of an image signal received by the flat panel display 120. The decoder 230 is used to analyze the fixed resolution of the flat panel display 120. The bypass controller 240 and the scaler unit 250 are used to scale the image signal to make the resolution of the image signal to match the fixed resolution of the flat panel display 120.
Firstly, the horizontal counter 210 receives a pixel clock (CLK) signal and a data enable (DE) signal, and counts a number of pulses of the CLK signal in a DE valid period. A counting result of the horizontal counter 210 represents a horizontal resolution of the image signal. The vertical counter 220 receives a vertical synchronization pulse (Vsync) signal, a horizontal synchronization pulse (Hsync) signal, and the DE signal, and counts a number of pulses of the DE signal between two adjacent vertical synchronization pulses. A counting result of the vertical counter 220 represents a vertical resolution of the image signal. The decoder 230 receives a panel size signal from a circuit of the flat panel display 120, and analyzes the panel size signal to obtain a fixed resolution of the flat panel display 120.
Secondly, the bypass controller 240 receives the resolution of the image signal and the fixed resolution of the flat panel display 120, compares the resolution of the image signal with the fixed resolution of the flat panel display 120, and outputs a bypass enable signal according to a comparing result. That is, if the resolution of the image signal matches the fixed resolution of the flat panel display 120, the bypass enable signal is output as a starting signal; otherwise, the bypass enable signal is output as an invalid signal.
Finally, the scaler unit 250 receives the image signal, the fixed resolution of the flat panel display 120, and the bypass enable signal. If the bypass enable signal is the starting signal, the scaler unit 250 outputs directly the image signal to a driving circuit of the flat panel display 120. If the bypass enable signal is the invalid signal, the scaler unit 250 scales the resolution of the image signal to match the fixed resolution of the flat panel display 120.
The above method for detecting the resolution of the image signal is directly counting the pulses of the CLK signal and the DE signal via the scaler control circuit 200. That is simple and convenient. The CLK signal and the DE signal are obtained by analyzing the image signal. However, the image signal is liable to be disturbed by other signals or circumstance factors when transmitted from the computer host 110 to the flat panel display 120. Thus, some undesired signals are liable to be superimposed on the CLK signal and the DE signal, namely, the CLK signal and the DE signal may include some undesired pulses. When the scaler control circuit 200 counts the pulses of the CLK signal and the DE signal, the undesired pulses are also counted. Therefore, the accuracy of the method for detecting the resolution of the image signal is low.
Therefore, an improved flat panel display is desired to overcome the above-described deficiencies. A method for detecting the resolution of the image signal is also desired.